1. Field of the Invention
The present invention relates to a semiconductor memory for storing a data sequence formed by adding redundancy bits identical with information bits to the information bits, methods of using and reading the semiconductor memory, and a storage medium storing the using and reading methods.
2. Description of the Related Art
Generally, when storage data is written in a memory cell array of a semiconductor memory including a nonvolatile semiconductor memory, error correction data of the storage data is added as redundancy bits. In reading out the storage data from the memory cell array, whether the contents have an error is checked. If an error is found, this error is corrected, and the corrected data is output as readout data. In this error correction, to be able to correct a t-bit error by adding m-bit error correction data to n-bit storage data, ##EQU1## must be satisfied.
According to this expression (1), to correct a 1-bit error which occurs most frequently, it is necessary to add m-bit error correction data meetin g EQU m+n+1.ltoreq.2.sup.m (2)
for t=1
According to this expression (2), to correct a 1-bit error for 1-bit storage data, error correction data having two or more bits is necessary. To correct 1-bit error for two bits storage data, error correction data having three or more bits is necessary.
As described above, to correct a 1-bit error for storage data, error correction data longer than the storage data is necessary. Therefore, the above method is extremely inefficient as an error correction method.
Additionally, for semiconductor memories in which 1-bit data, i.e., "0" or "1" is stored in each memory cell, a method of performing error correction with certain high efficiency has been developed. However, the development of multi-level (multi-valued) semiconductor memories in which data to be stored in each memory cell has two or more bits has not been accomplished yet, so no error correction method for these memories is known. Even if a certain correction method may have been proposed, the method is presumably inferior in efficiency to Hamming correction and the like because one element of a multi-level semiconductor memory stores a larger amount of information than that stored in one element of a single-level semiconductor memory.
Japanese Patent Laid-Open No. 6-282992 has disclosed a nonvolatile semiconductor memory which stores storage information together with a parity bit in a memory cell and thereby increases the capacity of the memory and improves the reliability of data. Also, Japanese Patent Laid-Open Nos. 2-146200 and 3-248251 have disclosed nonvolatile semiconductor memories with an error correction function. However, these methods require tedious operation of generating error vectors in error detection. In addition, these methods are techniques applicable only to common nonvolatile semiconductor memories. None of the patent specifications cited above refer to multi-level semiconductor memories.